TM DSG SiNT MOSFET with a inner gate and outer gate are shown with

Drain current (top) and subband energies (bottom) versus the n

TM DSG SiNT MOSFET with a inner gate and outer gate are shown with

ION/IOFF ratio comparison of this work with reports in literature

Sketch of possible architectures for tunnel FETs based on 2D

Effect of 3 nm gate length scaling in junctionless double

Anil VOHRA, Professor (Full), M.Sc., Ph.D

TM DSG SiNT MOSFET with a inner gate and outer gate are shown with

Anil VOHRA, Professor (Full), M.Sc., Ph.D

TM DSG SiNT MOSFET with a inner gate and outer gate are shown with

I On /I Off ratio comparison of this work with literature

ION/IOFF ratio comparison of this work with reports in literature